sb_ledda_ip $ yosys -p "synth_ice40 -top main -json hardware.json" leds.v main.v queue.v queue_pusher.v register.v reset_gen.v serial_tx.v sine_gen.v timing.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.38+113 (git sha1 30fead6d6, clang++ 15.0.0 -fPIC -Os) -- Parsing `leds.v' using frontend ` -vlog2k' -- sb_ledda_ip How to use it? sb_ledda_ip 1. Executing Verilog-2005 frontend: leds.v Parsing Verilog input from `leds.v' to AST representation. Storing AST representation for module `$abstract\leds'. Successfully finished Verilog frontend. -- Parsing `main.v' using frontend ` -vlog2k' -- 2. Executing Verilog-2005 frontend: main.v Parsing Verilog input from `main.v' to AST representation. Storing AST representation for module `$abstract\main'. sb_ledda_ip How to get it? sb_ledda_ip Successfully finished Verilog frontend. -- Parsing `queue.v' using frontend ` -vlog2k' -- 3. Executing Verilog-2005 frontend: queue.v Parsing Verilog input from `queue.v' to AST representation. Storing AST representation for module `$abstract\queue'. Successfully finished Verilog frontend. -- Parsing `queue_pusher.v' using frontend ` -vlog2k' -- sb_ledda_ip PasteShr sb_ledda_ip 4. Executing Verilog-2005 frontend: queue_pusher.v Parsing Verilog input from `queue_pusher.v' to AST representation. Storing AST representation for module `$abstract\queue_pusher'. Successfully finished Verilog frontend. -- Parsing `register.v' using frontend ` -vlog2k' -- 5. Executing Verilog-2005 frontend: register.v Parsing Verilog input from `register.v' to AST representation. sb_ledda_ip PasteShr sb_ledda_ip Storing AST representation for module `$abstract\register'. Successfully finished Verilog frontend. -- Parsing `reset_gen.v' using frontend ` -vlog2k' -- 6. Executing Verilog-2005 frontend: reset_gen.v Parsing Verilog input from `reset_gen.v' to AST representation. Storing AST representation for module `$abstract\reset_gen'. Successfully finished Verilog frontend. sb_ledda_ip How to get it? sb_ledda_ip -- Parsing `serial_tx.v' using frontend ` -vlog2k' -- 7. Executing Verilog-2005 frontend: serial_tx.v Parsing Verilog input from `serial_tx.v' to AST representation. Storing AST representation for module `$abstract\serial_tx'. Successfully finished Verilog frontend. -- Parsing `sine_gen.v' using frontend ` -vlog2k' -- 8. Executing Verilog-2005 frontend: sine_gen.v sb_ledda_ip How to get it? sb_ledda_ip Parsing Verilog input from `sine_gen.v' to AST representation. Storing AST representation for module `$abstract\sine_gen'. Successfully finished Verilog frontend. -- Parsing `timing.v' using frontend ` -vlog2k' -- 9. Executing Verilog-2005 frontend: timing.v Parsing Verilog input from `timing.v' to AST representation. Storing AST representation for module `$abstract\timing'. Successfully finished Verilog frontend. sb_ledda_ip How to get it? sb_ledda_ip -- Running command `synth_ice40 -top main -json hardware.json' -- 10. Executing SYNTH_ICE40 pass. 10.1. Executing Verilog-2005 frontend: /Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. sb_ledda_ip PasteShr sb_ledda_ip Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. sb_ledda_ip PasteShr sb_ledda_ip Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. sb_ledda_ip How to get it? sb_ledda_ip Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. sb_ledda_ip How to use it? sb_ledda_ip Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. sb_ledda_ip How to get it for free? sb_ledda_ip Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 10.2. Executing HIERARCHY pass (managing design hierarchy). sb_ledda_ip How to dowload it? sb_ledda_ip 10.3. Executing AST frontend in derive mode using pre-parsed AST for module `\main'. Generating RTLIL representation for module `\main'. 10.3.1. Analyzing design hierarchy.. Top module: \main Parameter \SERIAL_DIV = 104 10.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\serial_tx'. Parameter \SERIAL_DIV = 104 sb_ledda_ip PasteShr sb_ledda_ip Generating RTLIL representation for module `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000'. 10.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\queue'. Generating RTLIL representation for module `\queue'. 10.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\queue_pusher'. Generating RTLIL representation for module `\queue_pusher'. Parameter \SIZE = 17 10.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\register'. sb_ledda_ip How to use it? sb_ledda_ip Parameter \SIZE = 17 Generating RTLIL representation for module `$paramod\register\SIZE=s32'00000000000000000000000000010001'. 10.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\sine_gen'. Generating RTLIL representation for module `\sine_gen'. Parameter \SIZE = 24 10.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\register'. Parameter \SIZE = 24 Generating RTLIL representation for module `$paramod\register\SIZE=s32'00000000000000000000000000011000'. sb_ledda_ip How to get it for free? sb_ledda_ip 10.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\timing'. Generating RTLIL representation for module `\timing'. 10.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\leds'. Generating RTLIL representation for module `\leds'. 10.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\reset_gen'. Generating RTLIL representation for module `\reset_gen'. sb_ledda_ip How to get it for free? sb_ledda_ip 10.3.11. Analyzing design hierarchy.. Top module: \main Used module: $paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000 Used module: \queue Used module: \queue_pusher Used module: $paramod\register\SIZE=s32'00000000000000000000000000010001 Used module: \sine_gen Used module: $paramod\register\SIZE=s32'00000000000000000000000000011000 Used module: \timing Used module: \leds sb_ledda_ip How to use it? sb_ledda_ip Used module: \reset_gen 10.3.12. Analyzing design hierarchy.. Top module: \main Used module: $paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000 Used module: \queue Used module: \queue_pusher Used module: $paramod\register\SIZE=s32'00000000000000000000000000010001 Used module: \sine_gen Used module: $paramod\register\SIZE=s32'00000000000000000000000000011000 sb_ledda_ip PasteShr sb_ledda_ip Used module: \timing Used module: \leds Used module: \reset_gen Removing unused module `$abstract\timing'. Removing unused module `$abstract\sine_gen'. Removing unused module `$abstract\serial_tx'. Removing unused module `$abstract\reset_gen'. Removing unused module `$abstract\register'. Removing unused module `$abstract\queue_pusher'. Removing unused module `$abstract\queue'. sb_ledda_ip How to get it for free? sb_ledda_ip Removing unused module `$abstract\main'. Removing unused module `$abstract\leds'. Removed 9 unused modules. 10.4. Executing PROC pass (convert processes to netlists). 10.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 10.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). sb_ledda_ip PasteShr sb_ledda_ip Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1346$241 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1290$234 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1215$230 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1159$223 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1090$220 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1042$217 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:973$214 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:925$211 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:769$203 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:713$196 in module SB_DFFESS. sb_ledda_ip PasteShr sb_ledda_ip Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:638$192 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:582$185 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:513$182 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:465$179 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:396$176 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:348$173 in module SB_DFFSR. Marked 1 switch rules as full_case in process $proc$reset_gen.v:12$544 in module reset_gen. Marked 1 switch rules as full_case in process $proc$leds.v:33$539 in module leds. Marked 1 switch rules as full_case in process $proc$timing.v:36$513 in module timing. Marked 3 switch rules as full_case in process $proc$register.v:27$508 in module $paramod\register\SIZE=s32'00000000000000000000000000011000. sb_ledda_ip How to get it? sb_ledda_ip Marked 3 switch rules as full_case in process $proc$sine_gen.v:33$442 in module sine_gen. Marked 3 switch rules as full_case in process $proc$register.v:27$424 in module $paramod\register\SIZE=s32'00000000000000000000000000010001. Removed 1 dead cases from process $proc$queue_pusher.v:28$423 in module queue_pusher. Marked 2 switch rules as full_case in process $proc$queue_pusher.v:28$423 in module queue_pusher. Marked 4 switch rules as full_case in process $proc$queue.v:34$399 in module queue. Marked 5 switch rules as full_case in process $proc$serial_tx.v:20$388 in module $paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000. Removed a total of 1 dead cases. 10.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 21 redundant assignments. sb_ledda_ip PasteShr sb_ledda_ip Promoted 43 assignments to connections. 10.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$244'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$240'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$233'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$229'. sb_ledda_ip How to dowload it? sb_ledda_ip Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$222'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$219'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$216'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$213'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$210'. sb_ledda_ip How to use it? sb_ledda_ip Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$208'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$206'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$202'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$195'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$191'. sb_ledda_ip How to get it? sb_ledda_ip Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$184'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$181'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$178'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$175'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$172'. sb_ledda_ip How to dowload it? sb_ledda_ip Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$170'. Set init value: \Q = 1'0 Found init rule in `\reset_gen.$proc$reset_gen.v:10$547'. Set init value: \counter = 4'0000 10.4.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1346$241'. Found async reset \R in `\SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1215$230'. Found async reset \S in `\SB_DFFNS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1090$220'. sb_ledda_ip How to dowload it? sb_ledda_ip Found async reset \R in `\SB_DFFNR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:973$214'. Found async reset \S in `\SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:769$203'. Found async reset \R in `\SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:638$192'. Found async reset \S in `\SB_DFFS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:513$182'. Found async reset \R in `\SB_DFFR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:396$176'. 10.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. sb_ledda_ip How to use it? sb_ledda_ip 10.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\main.$proc$main.v:36$386'. Creating decoders for process `\SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$244'. Creating decoders for process `\SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1346$241'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$240'. Creating decoders for process `\SB_DFFNESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1290$234'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$233'. Creating decoders for process `\SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1215$230'. sb_ledda_ip How to get it? sb_ledda_ip 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$229'. Creating decoders for process `\SB_DFFNESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1159$223'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$222'. Creating decoders for process `\SB_DFFNS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1090$220'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$219'. Creating decoders for process `\SB_DFFNSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1042$217'. 1/1: $0\Q[0:0] sb_ledda_ip How to get it? sb_ledda_ip Creating decoders for process `\SB_DFFNR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$216'. Creating decoders for process `\SB_DFFNR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:973$214'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$213'. Creating decoders for process `\SB_DFFNSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:925$211'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$210'. Creating decoders for process `\SB_DFFNE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:882$209'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$208'. sb_ledda_ip How to dowload it? sb_ledda_ip Creating decoders for process `\SB_DFFN.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:846$207'. Creating decoders for process `\SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$206'. Creating decoders for process `\SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:769$203'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$202'. Creating decoders for process `\SB_DFFESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:713$196'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$195'. Creating decoders for process `\SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:638$192'. 1/1: $0\Q[0:0] sb_ledda_ip PasteShr sb_ledda_ip Creating decoders for process `\SB_DFFESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$191'. Creating decoders for process `\SB_DFFESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:582$185'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$184'. Creating decoders for process `\SB_DFFS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:513$182'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$181'. Creating decoders for process `\SB_DFFSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:465$179'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$178'. sb_ledda_ip How to use it? sb_ledda_ip Creating decoders for process `\SB_DFFR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:396$176'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$175'. Creating decoders for process `\SB_DFFSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:348$173'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$172'. Creating decoders for process `\SB_DFFE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:305$171'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$170'. Creating decoders for process `\SB_DFF.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:269$169'. sb_ledda_ip How to get it? sb_ledda_ip Creating decoders for process `\reset_gen.$proc$reset_gen.v:10$547'. Creating decoders for process `\reset_gen.$proc$reset_gen.v:12$544'. 1/2: $0\sys_reset[0:0] 2/2: $0\counter[3:0] Creating decoders for process `\leds.$proc$leds.v:33$539'. 1/1: $0\divider[15:0] Creating decoders for process `\timing.$proc$timing.v:36$513'. 1/7: $0\out_shift[0:0] 2/7: $0\in_rdy[0:0] 3/7: $0\in_shift[0:0] sb_ledda_ip How to get it for free? sb_ledda_ip 4/7: $0\bclk[0:0] 5/7: $0\lrclk[0:0] 6/7: $0\bit_slot[4:0] 7/7: $0\bit_phase[2:0] Creating decoders for process `$paramod\register\SIZE=s32'00000000000000000000000000011000.$proc$register.v:27$508'. 1/1: $0\data_out[23:0] Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$506'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$504'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$502'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$500'. sb_ledda_ip How to get it? sb_ledda_ip Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$498'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$496'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$494'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$492'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$490'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$488'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$486'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$484'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$482'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$480'. sb_ledda_ip How to dowload it? sb_ledda_ip Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$478'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:0$476'. Creating decoders for process `\sine_gen.$proc$sine_gen.v:33$442'. 1/3: $0\prescaler[0:0] 2/3: $0\step[5:0] 3/3: $0\sine_wave[15:0] Creating decoders for process `$paramod\register\SIZE=s32'00000000000000000000000000010001.$proc$register.v:27$424'. 1/1: $0\data_out[16:0] Creating decoders for process `\queue_pusher.$proc$queue_pusher.v:28$423'. 1/6: $0\byte3[7:0] sb_ledda_ip How to get it? sb_ledda_ip 2/6: $0\byte2[7:0] 3/6: $0\overrun_err[0:0] 4/6: $0\data_out[7:0] 5/6: $0\queue_wr_req[0:0] 6/6: $0\state[1:0] Creating decoders for process `\queue.$proc$queue.v:34$399'. 1/17: $3$memwr$\mem$queue.v:66$398_EN[7:0]$418 2/17: $3$memwr$\mem$queue.v:66$398_DATA[7:0]$417 3/17: $3$memwr$\mem$queue.v:66$398_ADDR[4:0]$416 4/17: $2$memwr$\mem$queue.v:66$398_EN[7:0]$408 sb_ledda_ip PasteShr sb_ledda_ip 5/17: $2$memwr$\mem$queue.v:66$398_DATA[7:0]$407 6/17: $2$memwr$\mem$queue.v:66$398_ADDR[4:0]$406 7/17: $0\wr_rdy[0:0] 8/17: $0\rd_rdy[0:0] 9/17: $0\rd_wr[0:0] 10/17: $1$memwr$\mem$queue.v:66$398_EN[7:0]$405 11/17: $1$memwr$\mem$queue.v:66$398_DATA[7:0]$404 12/17: $1$memwr$\mem$queue.v:66$398_ADDR[4:0]$403 13/17: $0\is_full[0:0] 14/17: $0\is_empty[0:0] sb_ledda_ip How to dowload it? sb_ledda_ip 15/17: $0\rd_ptr[4:0] 16/17: $0\wr_ptr[4:0] 17/17: $0\data_out[7:0] Creating decoders for process `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. 1/5: $0\timer[6:0] 2/5: $0\shifter[7:0] 3/5: $0\tx[0:0] 4/5: $0\queue_rd_req[0:0] 5/5: $0\state[4:0] sb_ledda_ip How to get it? sb_ledda_ip 10.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:87$441_EN' from process `\sine_gen.$proc$sine_gen.v:0$506'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:86$440_EN' from process `\sine_gen.$proc$sine_gen.v:0$504'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:85$439_EN' from process `\sine_gen.$proc$sine_gen.v:0$502'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:84$438_EN' from process `\sine_gen.$proc$sine_gen.v:0$500'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:83$437_EN' from process `\sine_gen.$proc$sine_gen.v:0$498'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:82$436_EN' from process `\sine_gen.$proc$sine_gen.v:0$496'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:81$435_EN' from process `\sine_gen.$proc$sine_gen.v:0$494'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:80$434_EN' from process `\sine_gen.$proc$sine_gen.v:0$492'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:79$433_EN' from process `\sine_gen.$proc$sine_gen.v:0$490'. sb_ledda_ip How to get it for free? sb_ledda_ip No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:78$432_EN' from process `\sine_gen.$proc$sine_gen.v:0$488'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:77$431_EN' from process `\sine_gen.$proc$sine_gen.v:0$486'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:76$430_EN' from process `\sine_gen.$proc$sine_gen.v:0$484'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:75$429_EN' from process `\sine_gen.$proc$sine_gen.v:0$482'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:74$428_EN' from process `\sine_gen.$proc$sine_gen.v:0$480'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:73$427_EN' from process `\sine_gen.$proc$sine_gen.v:0$478'. No latch inferred for signal `\sine_gen.$memwr$\mem$sine_gen.v:72$426_EN' from process `\sine_gen.$proc$sine_gen.v:0$476'. 10.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\main.\divider' using process `\main.$proc$main.v:36$386'. sb_ledda_ip How to get it for free? sb_ledda_ip created $dff cell `$procdff$967' with positive edge clock. Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1346$241'. created $adff cell `$procdff$968' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1290$234'. created $dff cell `$procdff$969' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1215$230'. created $adff cell `$procdff$970' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1159$223'. created $dff cell `$procdff$971' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1090$220'. sb_ledda_ip How to get it for free? sb_ledda_ip created $adff cell `$procdff$972' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1042$217'. created $dff cell `$procdff$973' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:973$214'. created $adff cell `$procdff$974' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:925$211'. created $dff cell `$procdff$975' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:882$209'. created $dff cell `$procdff$976' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:846$207'. sb_ledda_ip How to get it for free? sb_ledda_ip created $dff cell `$procdff$977' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:769$203'. created $adff cell `$procdff$978' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:713$196'. created $dff cell `$procdff$979' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:638$192'. created $adff cell `$procdff$980' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:582$185'. created $dff cell `$procdff$981' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:513$182'. sb_ledda_ip How to use it? sb_ledda_ip created $adff cell `$procdff$982' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:465$179'. created $dff cell `$procdff$983' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:396$176'. created $adff cell `$procdff$984' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:348$173'. created $dff cell `$procdff$985' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:305$171'. created $dff cell `$procdff$986' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:269$169'. sb_ledda_ip How to dowload it? sb_ledda_ip created $dff cell `$procdff$987' with positive edge clock. Creating register for signal `\reset_gen.\sys_reset' using process `\reset_gen.$proc$reset_gen.v:12$544'. created $dff cell `$procdff$988' with positive edge clock. Creating register for signal `\reset_gen.\counter' using process `\reset_gen.$proc$reset_gen.v:12$544'. created $dff cell `$procdff$989' with positive edge clock. Creating register for signal `\leds.\divider' using process `\leds.$proc$leds.v:33$539'. created $dff cell `$procdff$990' with positive edge clock. Creating register for signal `\timing.\bclk' using process `\timing.$proc$timing.v:36$513'. created $dff cell `$procdff$991' with positive edge clock. Creating register for signal `\timing.\lrclk' using process `\timing.$proc$timing.v:36$513'. sb_ledda_ip PasteShr sb_ledda_ip created $dff cell `$procdff$992' with positive edge clock. Creating register for signal `\timing.\in_shift' using process `\timing.$proc$timing.v:36$513'. created $dff cell `$procdff$993' with positive edge clock. Creating register for signal `\timing.\in_rdy' using process `\timing.$proc$timing.v:36$513'. created $dff cell `$procdff$994' with positive edge clock. Creating register for signal `\timing.\out_shift' using process `\timing.$proc$timing.v:36$513'. created $dff cell `$procdff$995' with positive edge clock. Creating register for signal `\timing.\bit_phase' using process `\timing.$proc$timing.v:36$513'. created $dff cell `$procdff$996' with positive edge clock. Creating register for signal `\timing.\bit_slot' using process `\timing.$proc$timing.v:36$513'. sb_ledda_ip How to get it for free? sb_ledda_ip created $dff cell `$procdff$997' with positive edge clock. Creating register for signal `$paramod\register\SIZE=s32'00000000000000000000000000011000.\data_out' using process `$paramod\register\SIZE=s32'00000000000000000000000000011000.$proc$register.v:27$508'. created $dff cell `$procdff$998' with positive edge clock. Creating register for signal `\sine_gen.\sine_wave' using process `\sine_gen.$proc$sine_gen.v:33$442'. created $dff cell `$procdff$999' with positive edge clock. Creating register for signal `\sine_gen.\prescaler' using process `\sine_gen.$proc$sine_gen.v:33$442'. created $dff cell `$procdff$1000' with positive edge clock. Creating register for signal `\sine_gen.\step' using process `\sine_gen.$proc$sine_gen.v:33$442'. created $dff cell `$procdff$1001' with positive edge clock. Creating register for signal `$paramod\register\SIZE=s32'00000000000000000000000000010001.\data_out' using process `$paramod\register\SIZE=s32'00000000000000000000000000010001.$proc$register.v:27$424'. sb_ledda_ip PasteShr sb_ledda_ip created $dff cell `$procdff$1002' with positive edge clock. Creating register for signal `\queue_pusher.\state' using process `\queue_pusher.$proc$queue_pusher.v:28$423'. created $dff cell `$procdff$1003' with positive edge clock. Creating register for signal `\queue_pusher.\queue_wr_req' using process `\queue_pusher.$proc$queue_pusher.v:28$423'. created $dff cell `$procdff$1004' with positive edge clock. Creating register for signal `\queue_pusher.\data_out' using process `\queue_pusher.$proc$queue_pusher.v:28$423'. created $dff cell `$procdff$1005' with positive edge clock. Creating register for signal `\queue_pusher.\overrun_err' using process `\queue_pusher.$proc$queue_pusher.v:28$423'. created $dff cell `$procdff$1006' with positive edge clock. Creating register for signal `\queue_pusher.\byte2' using process `\queue_pusher.$proc$queue_pusher.v:28$423'. sb_ledda_ip How to dowload it? sb_ledda_ip created $dff cell `$procdff$1007' with positive edge clock. Creating register for signal `\queue_pusher.\byte3' using process `\queue_pusher.$proc$queue_pusher.v:28$423'. created $dff cell `$procdff$1008' with positive edge clock. Creating register for signal `\queue.\data_out' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1009' with positive edge clock. Creating register for signal `\queue.\wr_rdy' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1010' with positive edge clock. Creating register for signal `\queue.\rd_rdy' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1011' with positive edge clock. Creating register for signal `\queue.\wr_ptr' using process `\queue.$proc$queue.v:34$399'. sb_ledda_ip How to get it? sb_ledda_ip created $dff cell `$procdff$1012' with positive edge clock. Creating register for signal `\queue.\rd_ptr' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1013' with positive edge clock. Creating register for signal `\queue.\rd_wr' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1014' with positive edge clock. Creating register for signal `\queue.\is_empty' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1015' with positive edge clock. Creating register for signal `\queue.\is_full' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1016' with positive edge clock. Creating register for signal `\queue.$memwr$\mem$queue.v:66$398_ADDR' using process `\queue.$proc$queue.v:34$399'. sb_ledda_ip PasteShr sb_ledda_ip created $dff cell `$procdff$1017' with positive edge clock. Creating register for signal `\queue.$memwr$\mem$queue.v:66$398_DATA' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1018' with positive edge clock. Creating register for signal `\queue.$memwr$\mem$queue.v:66$398_EN' using process `\queue.$proc$queue.v:34$399'. created $dff cell `$procdff$1019' with positive edge clock. Creating register for signal `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.\state' using process `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. created $dff cell `$procdff$1020' with positive edge clock. Creating register for signal `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.\queue_rd_req' using process `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. created $dff cell `$procdff$1021' with positive edge clock. Creating register for signal `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.\tx' using process `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. sb_ledda_ip How to get it for free? sb_ledda_ip created $dff cell `$procdff$1022' with positive edge clock. Creating register for signal `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.\shifter' using process `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. created $dff cell `$procdff$1023' with positive edge clock. Creating register for signal `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.\timer' using process `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. created $dff cell `$procdff$1024' with positive edge clock. 10.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 10.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `main.$proc$main.v:36$386'. sb_ledda_ip How to get it for free? sb_ledda_ip Removing empty process `SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$244'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1346$241'. Removing empty process `SB_DFFNES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1346$241'. Removing empty process `SB_DFFNESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$240'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1290$234'. Removing empty process `SB_DFFNESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1290$234'. Removing empty process `SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$233'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1215$230'. Removing empty process `SB_DFFNER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1215$230'. Removing empty process `SB_DFFNESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$229'. sb_ledda_ip How to get it? sb_ledda_ip Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1159$223'. Removing empty process `SB_DFFNESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1159$223'. Removing empty process `SB_DFFNS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$222'. Removing empty process `SB_DFFNS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1090$220'. Removing empty process `SB_DFFNSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$219'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1042$217'. Removing empty process `SB_DFFNSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:1042$217'. Removing empty process `SB_DFFNR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$216'. Removing empty process `SB_DFFNR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:973$214'. Removing empty process `SB_DFFNSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$213'. sb_ledda_ip How to get it for free? sb_ledda_ip Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:925$211'. Removing empty process `SB_DFFNSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:925$211'. Removing empty process `SB_DFFNE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$210'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:882$209'. Removing empty process `SB_DFFNE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:882$209'. Removing empty process `SB_DFFN.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$208'. Removing empty process `SB_DFFN.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:846$207'. Removing empty process `SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$206'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:769$203'. Removing empty process `SB_DFFES.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:769$203'. sb_ledda_ip How to dowload it? sb_ledda_ip Removing empty process `SB_DFFESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$202'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:713$196'. Removing empty process `SB_DFFESS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:713$196'. Removing empty process `SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$195'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:638$192'. Removing empty process `SB_DFFER.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:638$192'. Removing empty process `SB_DFFESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$191'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:582$185'. Removing empty process `SB_DFFESR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:582$185'. Removing empty process `SB_DFFS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$184'. sb_ledda_ip How to use it? sb_ledda_ip Removing empty process `SB_DFFS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:513$182'. Removing empty process `SB_DFFSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$181'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:465$179'. Removing empty process `SB_DFFSS.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:465$179'. Removing empty process `SB_DFFR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$178'. Removing empty process `SB_DFFR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:396$176'. Removing empty process `SB_DFFSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$175'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:348$173'. Removing empty process `SB_DFFSR.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:348$173'. Removing empty process `SB_DFFE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$172'. sb_ledda_ip How to get it? sb_ledda_ip Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:305$171'. Removing empty process `SB_DFFE.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:305$171'. Removing empty process `SB_DFF.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:0$170'. Removing empty process `SB_DFF.$proc$/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/ice40/cells_sim.v:269$169'. Removing empty process `reset_gen.$proc$reset_gen.v:10$547'. Found and cleaned up 1 empty switch in `\reset_gen.$proc$reset_gen.v:12$544'. Removing empty process `reset_gen.$proc$reset_gen.v:12$544'. Found and cleaned up 1 empty switch in `\leds.$proc$leds.v:33$539'. Removing empty process `leds.$proc$leds.v:33$539'. Found and cleaned up 1 empty switch in `\timing.$proc$timing.v:36$513'. sb_ledda_ip How to use it? sb_ledda_ip Removing empty process `timing.$proc$timing.v:36$513'. Found and cleaned up 4 empty switches in `$paramod\register\SIZE=s32'00000000000000000000000000011000.$proc$register.v:27$508'. Removing empty process `$paramod\register\SIZE=s32'00000000000000000000000000011000.$proc$register.v:27$508'. Removing empty process `sine_gen.$proc$sine_gen.v:0$506'. Removing empty process `sine_gen.$proc$sine_gen.v:0$504'. Removing empty process `sine_gen.$proc$sine_gen.v:0$502'. Removing empty process `sine_gen.$proc$sine_gen.v:0$500'. Removing empty process `sine_gen.$proc$sine_gen.v:0$498'. Removing empty process `sine_gen.$proc$sine_gen.v:0$496'. Removing empty process `sine_gen.$proc$sine_gen.v:0$494'. sb_ledda_ip How to dowload it? sb_ledda_ip Removing empty process `sine_gen.$proc$sine_gen.v:0$492'. Removing empty process `sine_gen.$proc$sine_gen.v:0$490'. Removing empty process `sine_gen.$proc$sine_gen.v:0$488'. Removing empty process `sine_gen.$proc$sine_gen.v:0$486'. Removing empty process `sine_gen.$proc$sine_gen.v:0$484'. Removing empty process `sine_gen.$proc$sine_gen.v:0$482'. Removing empty process `sine_gen.$proc$sine_gen.v:0$480'. Removing empty process `sine_gen.$proc$sine_gen.v:0$478'. Removing empty process `sine_gen.$proc$sine_gen.v:0$476'. Found and cleaned up 3 empty switches in `\sine_gen.$proc$sine_gen.v:33$442'. sb_ledda_ip PasteShr sb_ledda_ip Removing empty process `sine_gen.$proc$sine_gen.v:33$442'. Found and cleaned up 4 empty switches in `$paramod\register\SIZE=s32'00000000000000000000000000010001.$proc$register.v:27$424'. Removing empty process `$paramod\register\SIZE=s32'00000000000000000000000000010001.$proc$register.v:27$424'. Found and cleaned up 9 empty switches in `\queue_pusher.$proc$queue_pusher.v:28$423'. Removing empty process `queue_pusher.$proc$queue_pusher.v:28$423'. Found and cleaned up 4 empty switches in `\queue.$proc$queue.v:34$399'. Removing empty process `queue.$proc$queue.v:34$399'. Found and cleaned up 6 empty switches in `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. Removing empty process `$paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000.$proc$serial_tx.v:20$388'. Cleaned up 51 empty switches. sb_ledda_ip How to get it for free? sb_ledda_ip 10.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module main. Optimizing module reset_gen. Optimizing module leds. Optimizing module timing. Optimizing module $paramod\register\SIZE=s32'00000000000000000000000000011000. Optimizing module sine_gen. Optimizing module $paramod\register\SIZE=s32'00000000000000000000000000010001. sb_ledda_ip How to dowload it? sb_ledda_ip Optimizing module queue_pusher. Optimizing module queue. Optimizing module $paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000. 10.5. Executing FLATTEN pass (flatten design). Deleting now unused module reset_gen. Deleting now unused module leds. Deleting now unused module timing. sb_ledda_ip How to dowload it? sb_ledda_ip Deleting now unused module $paramod\register\SIZE=s32'00000000000000000000000000011000. Deleting now unused module sine_gen. Deleting now unused module $paramod\register\SIZE=s32'00000000000000000000000000010001. Deleting now unused module queue_pusher. Deleting now unused module queue. Deleting now unused module $paramod\serial_tx\SERIAL_DIV=s32'00000000000000000000000001101000. 10.6. Executing TRIBUF pass. sb_ledda_ip How to get it? sb_ledda_ip 10.7. Executing DEMINOUT pass (demote inout ports to input or output). 10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module main. 10.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 12 unused cells and 217 unused wires. sb_ledda_ip How to dowload it? sb_ledda_ip 10.10. Executing CHECK pass (checking for obvious problems). Checking module main... Found and reported 0 problems. 10.11. Executing OPT pass (performing simple optimizations). 10.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module main. sb_ledda_ip How to get it for free? sb_ledda_ip 10.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 57 cells. 10.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. sb_ledda_ip PasteShr sb_ledda_ip dead port 1/2 on $mux $flatten\queue.$procmux$752. dead port 1/2 on $mux $flatten\queue.$procmux$755. dead port 1/2 on $mux $flatten\queue.$procmux$761. dead port 1/2 on $mux $flatten\queue.$procmux$764. dead port 1/2 on $mux $flatten\queue.$procmux$770. dead port 1/2 on $mux $flatten\queue.$procmux$773. dead port 1/2 on $mux $flatten\queue.$procmux$779. dead port 1/2 on $mux $flatten\queue.$procmux$785. dead port 1/2 on $mux $flatten\queue.$procmux$791. Removed 9 multiplexer ports. sb_ledda_ip How to get it for free? sb_ledda_ip 10.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. Consolidated identical input bits for $mux cell $flatten\queue.$procmux$749: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\queue.$procmux$749_Y New ports: A=1'0, B=1'1, Y=$flatten\queue.$procmux$749_Y [0] New connections: $flatten\queue.$procmux$749_Y [7:1] = { $flatten\queue.$procmux$749_Y [0] $flatten\queue.$procmux$749_Y [0] $flatten\queue.$procmux$749_Y [0] $flatten\queue.$procmux$749_Y [0] $flatten\queue.$procmux$749_Y [0] $flatten\queue.$procmux$749_Y [0] $flatten\queue.$procmux$749_Y [0] } Optimizing cells in module \main. Consolidated identical input bits for $mux cell $flatten\queue.$procmux$776: sb_ledda_ip How to get it? sb_ledda_ip Old ports: A=$flatten\queue.$3$memwr$\mem$queue.v:66$398_EN[7:0]$418, B=8'00000000, Y=$flatten\queue.$procmux$776_Y New ports: A=$flatten\queue.$procmux$749_Y [0], B=1'0, Y=$flatten\queue.$procmux$776_Y [0] New connections: $flatten\queue.$procmux$776_Y [7:1] = { $flatten\queue.$procmux$776_Y [0] $flatten\queue.$procmux$776_Y [0] $flatten\queue.$procmux$776_Y [0] $flatten\queue.$procmux$776_Y [0] $flatten\queue.$procmux$776_Y [0] $flatten\queue.$procmux$776_Y [0] $flatten\queue.$procmux$776_Y [0] } Optimizing cells in module \main. Consolidated identical input bits for $mux cell $flatten\queue.$procmux$822: Old ports: A=$flatten\queue.$2$memwr$\mem$queue.v:66$398_EN[7:0]$408, B=8'00000000, Y=$flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 New ports: A=$flatten\queue.$procmux$776_Y [0], B=1'0, Y=$flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] New connections: $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [7:1] = { $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] $flatten\queue.$0$memwr$\mem$queue.v:66$398_EN[7:0]$402 [0] } Optimizing cells in module \main. Performed a total of 3 changes. sb_ledda_ip PasteShr sb_ledda_ip 10.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 3 cells. 10.11.6. Executing OPT_DFF pass (perform DFF optimizations). 10.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. sb_ledda_ip PasteShr sb_ledda_ip Removed 0 unused cells and 50 unused wires. 10.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module main. 10.11.9. Rerunning OPT passes. (Maybe there is more to do..) 10.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. sb_ledda_ip How to use it? sb_ledda_ip Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 10.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. New ctrl vector for $pmux cell $flatten\queue_pusher.$procmux$718: { $flatten\queue_pusher.$procmux$673_CMP $auto$opt_reduce.cc:134:opt_pmux$1036 $flatten\queue_pusher.$procmux$703_CMP } New ctrl vector for $pmux cell $flatten\serial_tx.$procmux$885: { $flatten\serial_tx.$procmux$898_CMP $flatten\serial_tx.$procmux$897_CMP $auto$opt_reduce.cc:134:opt_pmux$1038 } sb_ledda_ip How to get it for free? sb_ledda_ip New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$1037: { $flatten\serial_tx.$procmux$886_CMP $flatten\serial_tx.$procmux$890_CMP $flatten\serial_tx.$procmux$894_CMP } Optimizing cells in module \main. Performed a total of 3 changes. 10.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 0 cells. 10.11.13. Executing OPT_DFF pass (perform DFF optimizations). sb_ledda_ip How to get it for free? sb_ledda_ip 10.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. 10.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module main. 10.11.16. Rerunning OPT passes. (Maybe there is more to do..) 10.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. sb_ledda_ip PasteShr sb_ledda_ip Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 10.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. Performed a total of 0 changes. sb_ledda_ip PasteShr sb_ledda_ip 10.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 0 cells. 10.11.20. Executing OPT_DFF pass (perform DFF optimizations). 10.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. 10.11.22. Executing OPT_EXPR pass (perform const folding). sb_ledda_ip PasteShr sb_ledda_ip Optimizing module main. 10.11.23. Finished OPT passes. (There is nothing left to do.) 10.12. Executing FSM pass (extract and optimize FSM). 10.12.1. Executing FSM_DETECT pass (finding FSMs in design). Found FSM state register main.queue_pusher.state. 10.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). sb_ledda_ip How to use it? sb_ledda_ip Extracting FSM `\queue_pusher.state' from module `\main'. found $dff cell for state register: $flatten\queue_pusher.$procdff$1003 root of input selection tree: $flatten\queue_pusher.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \reset_gen.sys_reset found ctrl input: $flatten\queue_pusher.$procmux$703_CMP found ctrl input: $flatten\queue_pusher.$procmux$706_CMP found ctrl input: $flatten\queue_pusher.$procmux$709_CMP found ctrl input: $flatten\queue_pusher.$procmux$673_CMP found ctrl input: \queue.wr_rdy sb_ledda_ip How to get it? sb_ledda_ip found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: \timing.in_rdy found state code: 2'01 found ctrl output: $flatten\queue_pusher.$procmux$709_CMP found ctrl output: $flatten\queue_pusher.$procmux$706_CMP found ctrl output: $flatten\queue_pusher.$procmux$703_CMP found ctrl output: $flatten\queue_pusher.$procmux$673_CMP ctrl inputs: { \queue.wr_rdy \timing.in_rdy \reset_gen.sys_reset } sb_ledda_ip How to use it? sb_ledda_ip ctrl outputs: { $flatten\queue_pusher.$0\state[1:0] $flatten\queue_pusher.$procmux$673_CMP $flatten\queue_pusher.$procmux$703_CMP $flatten\queue_pusher.$procmux$706_CMP $flatten\queue_pusher.$procmux$709_CMP } transition: 2'00 3'-00 -> 2'00 6'001000 transition: 2'00 3'-10 -> 2'01 6'011000 transition: 2'00 3'--1 -> 2'00 6'001000 transition: 2'10 3'0-0 -> 2'10 6'100010 transition: 2'10 3'1-0 -> 2'11 6'110010 transition: 2'10 3'--1 -> 2'00 6'000010 transition: 2'01 3'0-0 -> 2'01 6'010001 transition: 2'01 3'1-0 -> 2'10 6'100001 transition: 2'01 3'--1 -> 2'00 6'000001 sb_ledda_ip How to use it? sb_ledda_ip transition: 2'11 3'0-0 -> 2'11 6'110100 transition: 2'11 3'1-0 -> 2'00 6'000100 transition: 2'11 3'--1 -> 2'00 6'000100 10.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\queue_pusher.state$1039' from module `\main'. 10.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 11 unused cells and 11 unused wires. sb_ledda_ip How to get it for free? sb_ledda_ip 10.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\queue_pusher.state$1039' from module `\main'. Removing unused output signal $flatten\queue_pusher.$0\state[1:0] [0]. Removing unused output signal $flatten\queue_pusher.$0\state[1:0] [1]. 10.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\queue_pusher.state$1039' from module `\main' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. sb_ledda_ip How to use it? sb_ledda_ip 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- 10.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\queue_pusher.state$1039' from module `main': ------------------------------------- sb_ledda_ip How to dowload it? sb_ledda_ip Information on FSM $fsm$\queue_pusher.state$1039 (\queue_pusher.state): Number of input signals: 3 Number of output signals: 4 Number of state bits: 4 Input signals: 0: \reset_gen.sys_reset 1: \timing.in_rdy 2: \queue.wr_rdy sb_ledda_ip How to use it? sb_ledda_ip Output signals: 0: $flatten\queue_pusher.$procmux$709_CMP 1: $flatten\queue_pusher.$procmux$706_CMP 2: $flatten\queue_pusher.$procmux$703_CMP 3: $flatten\queue_pusher.$procmux$673_CMP State encoding: 0: 4'---1 1: 4'--1- sb_ledda_ip How to use it? sb_ledda_ip 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'-00 -> 0 4'1000 1: 0 3'--1 -> 0 4'1000 2: 0 3'-10 -> 2 4'1000 3: 1 3'--1 -> 0 4'0010 4: 1 3'0-0 -> 1 4'0010 5: 1 3'1-0 -> 3 4'0010 sb_ledda_ip How to use it? sb_ledda_ip 6: 2 3'--1 -> 0 4'0001 7: 2 3'1-0 -> 1 4'0001 8: 2 3'0-0 -> 2 4'0001 9: 3 3'1-0 -> 0 4'0100 10: 3 3'--1 -> 0 4'0100 11: 3 3'0-0 -> 3 4'0100 ------------------------------------- 10.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). sb_ledda_ip How to get it? sb_ledda_ip Mapping FSM `$fsm$\queue_pusher.state$1039' from module `\main'. 10.13. Executing OPT pass (performing simple optimizations). 10.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module main. 10.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. sb_ledda_ip How to use it? sb_ledda_ip Removed a total of 4 cells. 10.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. sb_ledda_ip How to use it? sb_ledda_ip 10.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. Performed a total of 0 changes. 10.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 0 cells. 10.13.6. Executing OPT_DFF pass (perform DFF optimizations). sb_ledda_ip PasteShr sb_ledda_ip Adding SRST signal on $flatten\timing.$procdff$997 ($dff) from module main (D = $flatten\timing.$ternary$timing.v:47$518_Y [4:0], Q = \timing.bit_slot, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$1087 ($sdff) from module main (D = $flatten\timing.$add$timing.v:47$516_Y [4:0], Q = \timing.bit_slot). Adding SRST signal on $flatten\timing.$procdff$996 ($dff) from module main (D = $flatten\timing.$add$timing.v:46$514_Y [2:0], Q = \timing.bit_phase, rval = 3'000). Adding SRST signal on $flatten\timing.$procdff$995 ($dff) from module main (D = $flatten\timing.$logic_and$timing.v:52$535_Y, Q = \timing.out_shift, rval = 1'0). Adding SRST signal on $flatten\timing.$procdff$994 ($dff) from module main (D = $flatten\timing.$logic_and$timing.v:51$532_Y, Q = \timing.in_rdy, rval = 1'0). Adding SRST signal on $flatten\timing.$procdff$993 ($dff) from module main (D = $flatten\timing.$logic_and$timing.v:50$529_Y, Q = \timing.in_shift, rval = 1'0). Adding SRST signal on $flatten\timing.$procdff$992 ($dff) from module main (D = $flatten\timing.$ternary$timing.v:48$521_Y, Q = \timing.lrclk, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1097 ($sdff) from module main (D = $flatten\timing.$logic_not$timing.v:48$520_Y, Q = \timing.lrclk). Adding SRST signal on $flatten\timing.$procdff$991 ($dff) from module main (D = $flatten\timing.$logic_and$timing.v:49$524_Y, Q = \timing.bclk, rval = 1'0). Adding SRST signal on $flatten\sine_gen.$procdff$999 ($dff) from module main (D = $flatten\sine_gen.$procmux$651_Y, Q = \sine_gen.sine_wave, rval = 16'0000000000000000). sb_ledda_ip PasteShr sb_ledda_ip Adding EN signal on $auto$ff.cc:266:slice$1100 ($sdff) from module main (D = $flatten\sine_gen.$procmux$645_Y, Q = \sine_gen.sine_wave). Adding SRST signal on $flatten\sine_gen.$procdff$1001 ($dff) from module main (D = $flatten\sine_gen.$procmux$640_Y, Q = \sine_gen.step, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$1102 ($sdff) from module main (D = $flatten\sine_gen.$add$sine_gen.v:45$445_Y [5:0], Q = \sine_gen.step). Adding SRST signal on $flatten\sine_gen.$procdff$1000 ($dff) from module main (D = $flatten\sine_gen.$add$sine_gen.v:41$444_Y [0], Q = \sine_gen.prescaler, rval = 1'0). Adding SRST signal on $flatten\serial_tx.$procdff$1024 ($dff) from module main (D = $flatten\serial_tx.$procmux$885_Y, Q = \serial_tx.timer, rval = 7'0000000). Adding EN signal on $auto$ff.cc:266:slice$1109 ($sdff) from module main (D = $flatten\serial_tx.$procmux$885_Y, Q = \serial_tx.timer). Adding SRST signal on $flatten\serial_tx.$procdff$1023 ($dff) from module main (D = $flatten\serial_tx.$procmux$908_Y, Q = \serial_tx.shifter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1117 ($sdff) from module main (D = $flatten\serial_tx.$procmux$908_Y, Q = \serial_tx.shifter). Adding SRST signal on $flatten\serial_tx.$procdff$1022 ($dff) from module main (D = $flatten\serial_tx.$procmux$921_Y, Q = \serial_tx.tx, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$1127 ($sdff) from module main (D = $flatten\serial_tx.$procmux$921_Y, Q = \serial_tx.tx). sb_ledda_ip PasteShr sb_ledda_ip Adding SRST signal on $flatten\serial_tx.$procdff$1021 ($dff) from module main (D = $flatten\serial_tx.$procmux$940_Y, Q = \serial_tx.queue_rd_req, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1139 ($sdff) from module main (D = $flatten\serial_tx.$procmux$940_Y, Q = \serial_tx.queue_rd_req). Adding SRST signal on $flatten\serial_tx.$procdff$1020 ($dff) from module main (D = $flatten\serial_tx.$procmux$950_Y, Q = \serial_tx.state, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$1147 ($sdff) from module main (D = $flatten\serial_tx.$procmux$950_Y, Q = \serial_tx.state). Adding EN signal on $flatten\reset_gen.$procdff$989 ($dff) from module main (D = $flatten\reset_gen.$add$reset_gen.v:15$546_Y [3:0], Q = \reset_gen.counter). Adding SRST signal on $flatten\queue_pusher.$procdff$1008 ($dff) from module main (D = $flatten\queue_pusher.$procmux$672_Y, Q = \queue_pusher.byte3, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1160 ($sdff) from module main (D = \i2s_in.data_out [7:0], Q = \queue_pusher.byte3). Adding SRST signal on $flatten\queue_pusher.$procdff$1007 ($dff) from module main (D = $flatten\queue_pusher.$procmux$682_Y, Q = \queue_pusher.byte2, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1164 ($sdff) from module main (D = \i2s_in.data_out [15:8], Q = \queue_pusher.byte2). Adding SRST signal on $flatten\queue_pusher.$procdff$1005 ($dff) from module main (D = $flatten\queue_pusher.$procmux$702_Y, Q = \queue_pusher.data_out, rval = 8'00000000). sb_ledda_ip How to use it? sb_ledda_ip Adding EN signal on $auto$ff.cc:266:slice$1168 ($sdff) from module main (D = $flatten\queue_pusher.$procmux$702_Y, Q = \queue_pusher.data_out). Adding SRST signal on $flatten\queue_pusher.$procdff$1004 ($dff) from module main (D = $flatten\queue_pusher.$procmux$718_Y, Q = \queue_pusher.queue_wr_req, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1182 ($sdff) from module main (D = $flatten\queue_pusher.$procmux$718_Y, Q = \queue_pusher.queue_wr_req). Adding SRST signal on $flatten\queue.$procdff$1016 ($dff) from module main (D = $flatten\queue.$procmux$837_Y, Q = \queue.is_full, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1194 ($sdff) from module main (D = $flatten\queue.$procmux$837_Y, Q = \queue.is_full). Adding SRST signal on $flatten\queue.$procdff$1015 ($dff) from module main (D = $flatten\queue.$procmux$849_Y, Q = \queue.is_empty, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$1202 ($sdff) from module main (D = $flatten\queue.$procmux$849_Y, Q = \queue.is_empty). Adding SRST signal on $flatten\queue.$procdff$1014 ($dff) from module main (D = $flatten\queue.$procmux$816_Y, Q = \queue.rd_wr, rval = 1'0). Adding SRST signal on $flatten\queue.$procdff$1013 ($dff) from module main (D = $flatten\queue.$procmux$858_Y, Q = \queue.rd_ptr, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$1211 ($sdff) from module main (D = $flatten\queue.$add$queue.v:51$411_Y [4:0], Q = \queue.rd_ptr). sb_ledda_ip How to get it for free? sb_ledda_ip Adding SRST signal on $flatten\queue.$procdff$1012 ($dff) from module main (D = $flatten\queue.$procmux$867_Y, Q = \queue.wr_ptr, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$1215 ($sdff) from module main (D = $flatten\queue.$add$queue.v:67$419_Y [4:0], Q = \queue.wr_ptr). Adding SRST signal on $flatten\queue.$procdff$1011 ($dff) from module main (D = $flatten\queue.$procmux$805_Y, Q = \queue.rd_rdy, rval = 1'0). Adding SRST signal on $flatten\queue.$procdff$1010 ($dff) from module main (D = $flatten\queue.$procmux$797_Y, Q = \queue.wr_rdy, rval = 1'0). Adding SRST signal on $flatten\queue.$procdff$1009 ($dff) from module main (D = $flatten\queue.$procmux$876_Y, Q = \queue.data_out, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1229 ($sdff) from module main (D = $flatten\queue.$memrd$\mem$queue.v:50$410_DATA, Q = \queue.data_out). Adding SRST signal on $flatten\leds.$procdff$990 ($dff) from module main (D = $flatten\leds.$add$leds.v:39$540_Y [15:0], Q = \leds.divider, rval = 16'1111111111111111). Adding SRST signal on $flatten\i2s_out.$procdff$1002 ($dff) from module main (D = $flatten\i2s_out.$procmux$662_Y [16:1], Q = \i2s_out.data_out [16:1], rval = 16'0000000000000000). Adding SRST signal on $flatten\i2s_out.$procdff$1002 ($dff) from module main (D = $flatten\i2s_out.$procmux$659_Y [0], Q = \i2s_out.data_out [0], rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1235 ($sdff) from module main (D = \i2s_out.data_out [1], Q = \i2s_out.data_out [0]). sb_ledda_ip How to dowload it? sb_ledda_ip Adding EN signal on $auto$ff.cc:266:slice$1234 ($sdff) from module main (D = $flatten\i2s_out.$procmux$662_Y [16:1], Q = \i2s_out.data_out [16:1]). Adding SRST signal on $flatten\i2s_in.$procdff$998 ($dff) from module main (D = $flatten\i2s_in.$procmux$625_Y, Q = \i2s_in.data_out, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$1242 ($sdff) from module main (D = { \sensor_din \i2s_in.data_out [23:1] }, Q = \i2s_in.data_out). 10.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 51 unused cells and 63 unused wires. 10.13.8. Executing OPT_EXPR pass (perform const folding). sb_ledda_ip PasteShr sb_ledda_ip Optimizing module main. 10.13.9. Rerunning OPT passes. (Maybe there is more to do..) 10.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. sb_ledda_ip PasteShr sb_ledda_ip Removed 0 multiplexer ports. 10.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. Performed a total of 0 changes. 10.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. sb_ledda_ip How to dowload it? sb_ledda_ip Removed a total of 16 cells. 10.13.13. Executing OPT_DFF pass (perform DFF optimizations). 10.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 0 unused cells and 16 unused wires. 10.13.15. Executing OPT_EXPR pass (perform const folding). sb_ledda_ip How to dowload it? sb_ledda_ip Optimizing module main. 10.13.16. Rerunning OPT passes. (Maybe there is more to do..) 10.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. sb_ledda_ip PasteShr sb_ledda_ip 10.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. Performed a total of 0 changes. 10.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 0 cells. sb_ledda_ip PasteShr sb_ledda_ip 10.13.20. Executing OPT_DFF pass (perform DFF optimizations). 10.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. 10.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module main. 10.13.23. Finished OPT passes. (There is nothing left to do.) sb_ledda_ip How to get it? sb_ledda_ip 10.14. Executing WREDUCE pass (reducing word size of cells). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:72$460 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:73$461 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:74$462 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:75$463 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:76$464 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:77$465 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:78$466 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:79$467 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:80$468 (sine_gen.mem). sb_ledda_ip How to get it? sb_ledda_ip Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:81$469 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:82$470 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:83$471 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:84$472 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:85$473 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:86$474 (sine_gen.mem). Removed top 28 address bits (of 32) from memory init port main.$flatten\sine_gen.$meminit$\mem$sine_gen.v:87$475 (sine_gen.mem). Removed top 28 address bits (of 32) from memory read port main.$flatten\sine_gen.$memrd$\mem$sine_gen.v:51$448 (sine_gen.mem). Removed top 31 bits (of 32) from port B of cell main.$flatten\leds.$add$leds.v:39$540 ($add). Removed top 16 bits (of 32) from port Y of cell main.$flatten\leds.$add$leds.v:39$540 ($add). sb_ledda_ip How to use it? sb_ledda_ip Removed top 26 bits (of 32) from port B of cell main.$flatten\leds.$lt$leds.v:30$538 ($lt). Removed top 29 bits (of 32) from port B of cell main.$flatten\leds.$lt$leds.v:29$537 ($lt). Removed top 28 bits (of 32) from port B of cell main.$flatten\leds.$lt$leds.v:28$536 ($lt). Removed top 31 bits (of 32) from port B of cell main.$flatten\reset_gen.$add$reset_gen.v:15$546 ($add). Removed top 28 bits (of 32) from port Y of cell main.$flatten\reset_gen.$add$reset_gen.v:15$546 ($add). Removed top 28 bits (of 32) from port B of cell main.$flatten\reset_gen.$lt$reset_gen.v:13$545 ($lt). Removed top 27 bits (of 32) from port B of cell main.$flatten\timing.$le$timing.v:52$534 ($le). Removed top 1 bits (of 3) from port B of cell main.$flatten\timing.$eq$timing.v:51$530 ($eq). Removed top 27 bits (of 32) from port B of cell main.$flatten\timing.$le$timing.v:50$528 ($le). Removed top 31 bits (of 32) from port B of cell main.$flatten\timing.$ge$timing.v:50$526 ($ge). sb_ledda_ip How to get it for free? sb_ledda_ip Removed top 2 bits (of 3) from port B of cell main.$flatten\timing.$eq$timing.v:50$525 ($eq). Removed top 29 bits (of 32) from port B of cell main.$flatten\timing.$le$timing.v:49$523 ($le). Removed top 30 bits (of 32) from port B of cell main.$flatten\timing.$ge$timing.v:49$522 ($ge). Removed top 31 bits (of 32) from port B of cell main.$flatten\timing.$add$timing.v:47$516 ($add). Removed top 27 bits (of 32) from port Y of cell main.$flatten\timing.$add$timing.v:47$516 ($add). Removed top 31 bits (of 32) from port B of cell main.$flatten\timing.$add$timing.v:46$514 ($add). Removed top 29 bits (of 32) from port Y of cell main.$flatten\timing.$add$timing.v:46$514 ($add). Removed top 1 bits (of 2) from port B of cell main.$auto$opt_dff.cc:195:make_patterns_logic$1124 ($ne). Removed top 1 bits (of 2) from port B of cell main.$flatten\sine_gen.$procmux$648_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell main.$flatten\sine_gen.$ternary$sine_gen.v:57$459 ($mux). sb_ledda_ip How to get it? sb_ledda_ip Removed top 16 bits (of 32) from port A of cell main.$flatten\sine_gen.$neg$sine_gen.v:57$458 ($neg). Removed top 16 bits (of 32) from port Y of cell main.$flatten\sine_gen.$neg$sine_gen.v:57$458 ($neg). Removed top 16 bits (of 32) from mux cell main.$flatten\sine_gen.$ternary$sine_gen.v:51$451 ($mux). Removed top 27 bits (of 32) from port A of cell main.$flatten\sine_gen.$sub$sine_gen.v:51$449 ($sub). Removed top 28 bits (of 32) from port Y of cell main.$flatten\sine_gen.$sub$sine_gen.v:51$449 ($sub). Removed top 4 bits (of 5) from port A of cell main.$flatten\sine_gen.$sub$sine_gen.v:51$449 ($sub). Removed top 31 bits (of 32) from port B of cell main.$flatten\sine_gen.$add$sine_gen.v:45$445 ($add). Removed top 26 bits (of 32) from port Y of cell main.$flatten\sine_gen.$add$sine_gen.v:45$445 ($add). Removed top 31 bits (of 32) from port B of cell main.$flatten\sine_gen.$add$sine_gen.v:41$444 ($add). Removed top 31 bits (of 32) from port Y of cell main.$flatten\sine_gen.$add$sine_gen.v:41$444 ($add). sb_ledda_ip How to use it? sb_ledda_ip Removed top 31 bits (of 32) from port B of cell main.$flatten\sine_gen.$lt$sine_gen.v:39$443 ($lt). Removed top 1 bits (of 2) from port B of cell main.$auto$opt_dff.cc:195:make_patterns_logic$1136 ($ne). Removed top 31 bits (of 32) from port B of cell main.$flatten\queue.$add$queue.v:67$419 ($add). Removed top 26 bits (of 32) from port Y of cell main.$flatten\queue.$add$queue.v:67$419 ($add). Removed top 31 bits (of 32) from port B of cell main.$flatten\queue.$add$queue.v:51$411 ($add). Removed top 26 bits (of 32) from port Y of cell main.$flatten\queue.$add$queue.v:51$411 ($add). Removed top 1 bits (of 2) from port B of cell main.$auto$opt_dff.cc:195:make_patterns_logic$1156 ($ne). Removed top 1 bits (of 2) from port B of cell main.$auto$opt_dff.cc:195:make_patterns_logic$1175 ($ne). Removed top 1 bits (of 2) from port B of cell main.$auto$opt_dff.cc:195:make_patterns_logic$1177 ($ne). Removed top 1 bits (of 2) from port B of cell main.$auto$opt_dff.cc:195:make_patterns_logic$1179 ($ne). sb_ledda_ip How to dowload it? sb_ledda_ip Removed top 1 bits (of 2) from port B of cell main.$auto$opt_dff.cc:195:make_patterns_logic$1191 ($ne). Removed top 4 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$897_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP7 ($eq). Removed top 1 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP6 ($eq). Removed top 2 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP5 ($eq). Removed top 2 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP4 ($eq). Removed top 2 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP3 ($eq). Removed top 2 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP2 ($eq). Removed top 3 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP1 ($eq). Removed top 3 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$894_CMP0 ($eq). sb_ledda_ip How to use it? sb_ledda_ip Removed top 1 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$890_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell main.$flatten\serial_tx.$procmux$886_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell main.$flatten\serial_tx.$add$serial_tx.v:54$393 ($add). Removed top 25 bits (of 32) from port Y of cell main.$flatten\serial_tx.$add$serial_tx.v:54$393 ($add). Removed top 31 bits (of 32) from port B of cell main.$flatten\serial_tx.$add$serial_tx.v:52$392 ($add). Removed top 27 bits (of 32) from port Y of cell main.$flatten\serial_tx.$add$serial_tx.v:52$392 ($add). Removed top 25 bits (of 32) from port B of cell main.$flatten\serial_tx.$ge$serial_tx.v:48$389 ($ge). Removed top 16 bits (of 32) from wire main.$flatten\leds.$add$leds.v:39$540_Y. Removed top 26 bits (of 32) from wire main.$flatten\queue.$add$queue.v:51$411_Y. Removed top 26 bits (of 32) from wire main.$flatten\queue.$add$queue.v:67$419_Y. sb_ledda_ip How to get it for free? sb_ledda_ip Removed top 28 bits (of 32) from wire main.$flatten\reset_gen.$add$reset_gen.v:15$546_Y. Removed top 27 bits (of 32) from wire main.$flatten\serial_tx.$add$serial_tx.v:52$392_Y. Removed top 25 bits (of 32) from wire main.$flatten\serial_tx.$add$serial_tx.v:54$393_Y. Removed top 6 bits (of 7) from wire main.$flatten\serial_tx.$procmux$885_Y. Removed top 31 bits (of 32) from wire main.$flatten\sine_gen.$add$sine_gen.v:41$444_Y. Removed top 26 bits (of 32) from wire main.$flatten\sine_gen.$add$sine_gen.v:45$445_Y. Removed top 16 bits (of 32) from wire main.$flatten\sine_gen.$extend$sine_gen.v:51$450_Y. Removed top 16 bits (of 32) from wire main.$flatten\sine_gen.$neg$sine_gen.v:57$458_Y. Removed top 28 bits (of 32) from wire main.$flatten\sine_gen.$sub$sine_gen.v:51$449_Y. Removed top 16 bits (of 32) from wire main.$flatten\sine_gen.$ternary$sine_gen.v:51$451_Y. sb_ledda_ip PasteShr sb_ledda_ip Removed top 16 bits (of 32) from wire main.$flatten\sine_gen.$ternary$sine_gen.v:57$459_Y. 10.15. Executing PEEPOPT pass (run peephole optimizers). 10.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 0 unused cells and 14 unused wires. 10.17. Executing SHARE pass (SAT-based resource sharing). sb_ledda_ip How to dowload it? sb_ledda_ip Found 2 cells in module main that may be considered for resource sharing. Analyzing resource sharing options for $flatten\sine_gen.$memrd$\mem$sine_gen.v:51$448 ($memrd): Found 2 activation_patterns using ctrl signal { $flatten\sine_gen.$eq$sine_gen.v:51$447_Y $flatten\sine_gen.$procmux$646_CMP $flatten\sine_gen.$procmux$648_CMP }. Found 1 candidates: $flatten\sine_gen.$memrd$\mem$sine_gen.v:48$446 Analyzing resource sharing with $flatten\sine_gen.$memrd$\mem$sine_gen.v:48$446 ($memrd): Found 2 activation_patterns using ctrl signal { $flatten\sine_gen.$procmux$647_CMP $flatten\sine_gen.$procmux$649_CMP }. Activation pattern for cell $flatten\sine_gen.$memrd$\mem$sine_gen.v:51$448: { $flatten\sine_gen.$eq$sine_gen.v:51$447_Y $flatten\sine_gen.$procmux$648_CMP } = 2'01 Activation pattern for cell $flatten\sine_gen.$memrd$\mem$sine_gen.v:51$448: { $flatten\sine_gen.$eq$sine_gen.v:51$447_Y $flatten\sine_gen.$procmux$646_CMP } = 2'01 Activation pattern for cell $flatten\sine_gen.$memrd$\mem$sine_gen.v:48$446: $flatten\sine_gen.$procmux$649_CMP = 1'1 Activation pattern for cell $flatten\sine_gen.$memrd$\mem$sine_gen.v:48$446: $flatten\sine_gen.$procmux$647_CMP = 1'1 sb_ledda_ip PasteShr sb_ledda_ip Size of SAT problem: 0 cells, 61 variables, 155 clauses According to the SAT solver this pair of cells can be shared. Activation signal for $flatten\sine_gen.$memrd$\mem$sine_gen.v:48$446: $auto$share.cc:987:make_cell_activation_logic$1261 New cell: $auto$share.cc:711:make_supercell$1263 ($memrd) Analyzing resource sharing options for $auto$share.cc:711:make_supercell$1263 ($memrd): Found 4 activation_patterns using ctrl signal { $flatten\sine_gen.$eq$sine_gen.v:51$447_Y $flatten\sine_gen.$procmux$646_CMP $flatten\sine_gen.$procmux$647_CMP $flatten\sine_gen.$procmux$648_CMP $flatten\sine_gen.$procmux$649_CMP }. No candidates found. Removing 2 cells in module main: Removing cell $flatten\sine_gen.$memrd$\mem$sine_gen.v:48$446 ($memrd). Removing cell $flatten\sine_gen.$memrd$\mem$sine_gen.v:51$448 ($memrd). sb_ledda_ip How to get it? sb_ledda_ip 10.18. Executing TECHMAP pass (map to technology primitives). 10.18.1. Executing Verilog-2005 frontend: /Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/Users/user/.apio/packages/tools-oss-cad-suite/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 10.18.2. Continuing TECHMAP pass. Using template $paramod$fd3a338331ce77d5c60504e1108b754e9b73ee37\_90_lut_cmp_ for cells of type $lt. sb_ledda_ip How to dowload it? sb_ledda_ip Using template $paramod$0d00cc40e311bf8a4e7352182cb125b78699faba\_90_lut_cmp_ for cells of type $le. Using template $paramod$c9a92e14d98ab383d8fbb820f90777798d53de2a\_90_lut_cmp_ for cells of type $ge. Using template $paramod$3cf7fc95a8b07135f0b761be10c473af5eaaef49\_90_lut_cmp_ for cells of type $lt. No more expansions possible. 10.19. Executing OPT_EXPR pass (perform const folding). Optimizing module main. sb_ledda_ip How to use it? sb_ledda_ip 10.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 0 unused cells and 15 unused wires. 10.21. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module main: creating $macc model for $add$main.v:37$387 ($add). creating $macc model for $flatten\leds.$add$leds.v:39$540 ($add). creating $macc model for $flatten\queue.$add$queue.v:51$411 ($add). sb_ledda_ip How to get it? sb_ledda_ip creating $macc model for $flatten\queue.$add$queue.v:67$419 ($add). creating $macc model for $flatten\reset_gen.$add$reset_gen.v:15$546 ($add). creating $macc model for $flatten\serial_tx.$add$serial_tx.v:52$392 ($add). creating $macc model for $flatten\serial_tx.$add$serial_tx.v:54$393 ($add). creating $macc model for $flatten\sine_gen.$add$sine_gen.v:41$444 ($add). creating $macc model for $flatten\sine_gen.$add$sine_gen.v:45$445 ($add). creating $macc model for $flatten\sine_gen.$neg$sine_gen.v:54$453 ($neg). creating $macc model for $flatten\sine_gen.$neg$sine_gen.v:57$458 ($neg). creating $macc model for $flatten\sine_gen.$sub$sine_gen.v:51$449 ($sub). creating $macc model for $flatten\timing.$add$timing.v:46$514 ($add). sb_ledda_ip How to get it for free? sb_ledda_ip creating $macc model for $flatten\timing.$add$timing.v:47$516 ($add). creating $alu model for $macc $flatten\timing.$add$timing.v:47$516. creating $alu model for $macc $flatten\timing.$add$timing.v:46$514. creating $alu model for $macc $flatten\sine_gen.$sub$sine_gen.v:51$449. creating $alu model for $macc $flatten\sine_gen.$neg$sine_gen.v:57$458. creating $alu model for $macc $flatten\sine_gen.$neg$sine_gen.v:54$453. creating $alu model for $macc $flatten\sine_gen.$add$sine_gen.v:45$445. creating $alu model for $macc $flatten\sine_gen.$add$sine_gen.v:41$444. creating $alu model for $macc $flatten\serial_tx.$add$serial_tx.v:54$393. creating $alu model for $macc $flatten\serial_tx.$add$serial_tx.v:52$392. sb_ledda_ip PasteShr sb_ledda_ip creating $alu model for $macc $flatten\reset_gen.$add$reset_gen.v:15$546. creating $alu model for $macc $flatten\queue.$add$queue.v:67$419. creating $alu model for $macc $flatten\queue.$add$queue.v:51$411. creating $alu model for $macc $flatten\leds.$add$leds.v:39$540. creating $alu model for $macc $add$main.v:37$387. creating $alu model for $flatten\leds.$lt$leds.v:28$536 ($lt): new $alu creating $alu model for $flatten\leds.$lt$leds.v:29$537 ($lt): new $alu creating $alu model for $flatten\leds.$lt$leds.v:30$538 ($lt): new $alu creating $alu model for $flatten\serial_tx.$ge$serial_tx.v:48$389 ($ge): new $alu creating $alu model for $flatten\timing.$ge$timing.v:50$526 ($ge): new $alu sb_ledda_ip How to get it for free? sb_ledda_ip creating $alu model for $flatten\timing.$le$timing.v:50$528 ($le): new $alu creating $alu model for $flatten\timing.$le$timing.v:52$534 ($le): new $alu creating $alu model for $flatten\timing.$eq$timing.v:51$531 ($eq): merged with $flatten\timing.$le$timing.v:50$528. creating $alu cell for $flatten\timing.$le$timing.v:52$534: $auto$alumacc.cc:485:replace_alu$1283 creating $alu cell for $flatten\timing.$le$timing.v:50$528, $flatten\timing.$eq$timing.v:51$531: $auto$alumacc.cc:485:replace_alu$1296 creating $alu cell for $flatten\serial_tx.$ge$serial_tx.v:48$389: $auto$alumacc.cc:485:replace_alu$1309 creating $alu cell for $flatten\leds.$lt$leds.v:30$538: $auto$alumacc.cc:485:replace_alu$1322 creating $alu cell for $flatten\leds.$lt$leds.v:29$537: $auto$alumacc.cc:485:replace_alu$1333 creating $alu cell for $flatten\leds.$lt$leds.v:28$536: $auto$alumacc.cc:485:replace_alu$1344 creating $alu cell for $add$main.v:37$387: $auto$alumacc.cc:485:replace_alu$1355 sb_ledda_ip How to dowload it? sb_ledda_ip creating $alu cell for $flatten\leds.$add$leds.v:39$540: $auto$alumacc.cc:485:replace_alu$1358 creating $alu cell for $flatten\queue.$add$queue.v:51$411: $auto$alumacc.cc:485:replace_alu$1361 creating $alu cell for $flatten\queue.$add$queue.v:67$419: $auto$alumacc.cc:485:replace_alu$1364 creating $alu cell for $flatten\reset_gen.$add$reset_gen.v:15$546: $auto$alumacc.cc:485:replace_alu$1367 creating $alu cell for $flatten\serial_tx.$add$serial_tx.v:52$392: $auto$alumacc.cc:485:replace_alu$1370 creating $alu cell for $flatten\serial_tx.$add$serial_tx.v:54$393: $auto$alumacc.cc:485:replace_alu$1373 creating $alu cell for $flatten\sine_gen.$add$sine_gen.v:41$444: $auto$alumacc.cc:485:replace_alu$1376 creating $alu cell for $flatten\sine_gen.$add$sine_gen.v:45$445: $auto$alumacc.cc:485:replace_alu$1379 creating $alu cell for $flatten\sine_gen.$neg$sine_gen.v:54$453: $auto$alumacc.cc:485:replace_alu$1382 creating $alu cell for $flatten\sine_gen.$neg$sine_gen.v:57$458: $auto$alumacc.cc:485:replace_alu$1385 sb_ledda_ip PasteShr sb_ledda_ip creating $alu cell for $flatten\sine_gen.$sub$sine_gen.v:51$449: $auto$alumacc.cc:485:replace_alu$1388 creating $alu cell for $flatten\timing.$add$timing.v:46$514: $auto$alumacc.cc:485:replace_alu$1391 creating $alu cell for $flatten\timing.$ge$timing.v:50$526: $auto$alumacc.cc:485:replace_alu$1394 creating $alu cell for $flatten\timing.$add$timing.v:47$516: $auto$alumacc.cc:485:replace_alu$1403 created 21 $alu and 0 $macc cells. 10.22. Executing OPT pass (performing simple optimizations). 10.22.1. Executing OPT_EXPR pass (perform const folding). Optimizing module main. sb_ledda_ip How to get it for free? sb_ledda_ip 10.22.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 1 cells. 10.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. sb_ledda_ip How to use it? sb_ledda_ip Analyzing evaluation results. Removed 0 multiplexer ports. 10.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. Performed a total of 0 changes. 10.22.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. sb_ledda_ip PasteShr sb_ledda_ip Removed a total of 0 cells. 10.22.6. Executing OPT_DFF pass (perform DFF optimizations). 10.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 0 unused cells and 11 unused wires. 10.22.8. Executing OPT_EXPR pass (perform const folding). sb_ledda_ip How to use it? sb_ledda_ip Optimizing module main. 10.22.9. Rerunning OPT passes. (Maybe there is more to do..) 10.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \main.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. sb_ledda_ip How to use it? sb_ledda_ip 10.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \main. Performed a total of 0 changes. 10.22.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\main'. Removed a total of 0 cells. sb_ledda_ip PasteShr sb_ledda_ip 10.22.13. Executing OPT_DFF pass (perform DFF optimizations). 10.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. 10.22.15. Executing OPT_EXPR pass (perform const folding). Optimizing module main. 10.22.16. Finished OPT passes. (There is nothing left to do.) sb_ledda_ip How to dowload it? sb_ledda_ip 10.23. Executing MEMORY pass. 10.23.1. Executing OPT_MEM pass (optimize memories). main.sine_gen.mem: removing const-0 lane 15 Performed a total of 1 transformations. 10.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 10.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). sb_ledda_ip PasteShr sb_ledda_ip Analyzing main.queue.mem write port 0. 10.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 10.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\queue.mem'[0] in module `\main': merging output FF to cell. Write port 0: don't care on collision. Checking read port `\sine_gen.mem'[0] in module `\main': no output FF found. Checking read port address `\sine_gen.mem'[0] in module `\main': no address FF found. sb_ledda_ip How to get it? sb_ledda_ip 10.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. Removed 1 unused cells and 9 unused wires. 10.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 10.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. sb_ledda_ip How to get it? sb_ledda_ip 10.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. 10.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 10.24. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \main.. 10.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). ERROR: +/ice40/brams.txt:1: unknown top-level item `bram`. sb_ledda_ip PasteShr sb_ledda_ip sb_ledda_ip